Semiconductor Technology

The key to the fantastic productivity increases over the last 40 years, semiconductors are ubiquitous. The historical productivity gains are founded on the doubling of transistors per semiconductor device every couple of years. This trend is known as Moore's Law and is depicted in Figure 1. While the progress has been challenging, it has been consistent: major technological breakthroughs have been accomplished in a matter-of-fact manner. One example is the challenging realtionship between the wavelength of light and the feature size. Figure 2 depicts the wavelength of light (y- axis) the feature size (y-axis also) versus the year of first manufacturing for the latter. The very interesting transition that occurred in 1995 was that the feature sizes of devices became smaller than the wavelength of the light employed to image them.

Why are the features so small? Each succeeding generation of devices is more complex and more powerful because there are more transistors that provide the ability to do more functions. As more and more functions are added to devices, the complexity of the circuitry requires an increasing number of connections. Figure 3, which is from the International Technology Roadmap for Semiconductors (ITRS) roadmap, indicates the levels of a semiconductor device. The bottom most levels are where the actual devices are located. The upper levels provide interconnection of the various functions to develop the functionality of the devices. In order for the density of the functions to increase, the size of the features decreases. [A driving force that has propelled the semiconductor industry is an almost constant cost per square centimeter over time as shown in Figure 4.] The current minimum feature sizes of the latest devices are less than 100 nanometers (nm), which many consider the "nano realm." [cf. "nano technology" for a differing view.] The real issues revolve around the need for new device structures that perform predictably as dimensions approach 10nm. There are four main areas of technology challenge - Front End Processes, Interconnect, Lithography, and Metrology - with the first three directly impacting device manufacturing.

Semiconductors - The Future

The process of Semiconductor manufacturing can be considered to consist of three fundamental groupings of technology: Front End Processes, Interconnect, and Lithography. Metrology is required to evaluate the manufacturing process to ensure that tolerances are being achieved. The interplay of all these elements come together in the manufacturing process. This is only the beginning of the total process to produce the devices that are a fundamental requirement of modern life.

All semiconductor processing is done on wafers, will hundreds of devices on each wafer that need to be tested after manufacturing, singulated into individual devices, and packaged before the process is done.

Front End processes (FEP)

FEP has a critical challenge. Traditionally, shrinking transistors required improvements in materials, such as developing High-K materials for better performance. However, the material properties will become a challenge for probably the 32nm technology generation. Novel designs that are being investigated are shown from the ITRS in Figure 5.


Interconnect can be viewed as the interconnection highways for moving signals around the device. "Barrier engineering including construction of very thin and low-resistive barrier metal, as well as efficient "pore sealing" for low-K material, is essential to achieve high conductivity in a narrow copper interconnect." [ITRS 2005] While there is a need for novel materials to provide improved insulation, there are additional problems from the nano realm that will need to be resolved. When line widths decrease to about 40nm, a new phenomenon influences the performances of the copper conductors: the conductivity of the copper lines is dependent on the grain size and orientation. In other words, additional controls must be added, in the future, to ensure that the smallest lines have the same properties.

Lithography (Litho)

Litho is the mechanism for creating the minute images that define the dimensions of the features that make the devices operate properly. The challenges for future litho are the ability to image large volumes of devices quickly. Since the features are sub-wavelength, many techniques are being employed to enhance the ability of the existing technologies. In addition, new imaging approaches are being considered. The evaluation of the feasibility of new technologies prior to their being fully developed creates some significant challenges and many opportunities for errors.

⇒ Supporting Technology


Metrology is the key to repeatable manufacturing. If one can not measure a feature, one can not reliably manufacture it. With measurement requirements of critical dimensions having tolerances of 1nm (three sigma), new approaches are required to perform measurements accurately, quickly, and with a high degree of precision.


The key to being able to manufacture new devices with improved technology is the ability to stay on the productivity cost for function curve shown in Figure 4. The history of the semiconductor industry has been to evolve through developing new materials and new processes. As the technology required becomes more sophisticated, the opportunities to estimate incorrectly increase.

The Challenge

With the rapid technology advancement that is being experienced in semiconductors, major research and development efforts must be evaluated in light of the projected life of the results. Figure 6 shows data on the life of Intel's microprocessors from the initial 286 device until the microprocessors of 2000. The fact that is obvious from the figure is that the life cycle of devices has rapidly decreased from 7 years to 6 to 9 months! With this being the trend of the semiconductor industry, the risks are becoming greater. The evaluation of decisions to move forward with major investments needs to consider the industry perspective from an overall view of the industry.

Probably the most discussed and least understood element of the technology equation is cost. An elegant solution to a technology issue that is unaffordable is not a solution. Similarly, an apparent cost-effective solution that has significant yield losses or high rework later in the process, is not cost-effective. Driving entry cost high to develop a barrier to keep competitors out only encourages them to find alternative and lower cost entry points. Evaluation of the options must include the financial consequences of decisions. Failure to consider them will result in ultimate failure. For over the last decade, TFI personnel have been involved in semiconductor technology cost analysis. AND, our results have been proven accurate projections of technology introduction.

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